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A library for Logic Circuit Simulation developed in 100% c++. The ultimate aim of LCS is to become a thorough hardware description library, matching the functionality of the Verilog hardware description language, while keeping the usage (and syntax) as intuitive as possible.
A framework for building computer system simulations. Specifically, a simulation is comprised of a collection of loosely coupled components. Simulated systems may range from a CPU's instruction set to a large multi-processor embedded system. [Open source, GPL with changes].
A lean object oriented C++ library for discrete event based simulations. It scales to millions of simulateed objects, has no external dependencies and can be embedded into other applications.
A framework for building computer system simulations. Specifically, a simulation is comprised of a collection of loosely coupled components. Simulated systems may range from a CPU's instruction set to a large multi-processor embedded system. [Open source, GPL with changes].
A lean object oriented C++ library for discrete event based simulations. It scales to millions of simulateed objects, has no external dependencies and can be embedded into other applications.
A library for Logic Circuit Simulation developed in 100% c++. The ultimate aim of LCS is to become a thorough hardware description library, matching the functionality of the Verilog hardware description language, while keeping the usage (and syntax) as intuitive as possible.
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September 24, 2018 at 5:15:08 UTC
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Regional: North America: Canada: Society and Culture: Organizations
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